Server: Microsoft-IIS/3.0 Date: Fri, 21 Nov 1997 05:15:38 GMT Content-Type: text/html OrCAD FPGA Design with Express OrCAD, Inc.
OrCAD FPGA Design with Express

Develop a high level of proficiency designing FPGAs with OrCAD ExpressTM in five days. The OrCAD FPGA design with Express workshop accelerates productivity with relevant, valuable instruction in FPGA design methodology and VHDL, as well as training in OrCAD Express. The workshop is taught by experienced EDA consultants who understand real-world design applications and engineering practices.

Workshop Overview

This five-day hands-on workshop takes you through each stage of the design process from design entry, VHDL synthesis and optimization, and functional and timing simulation; to designing field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs).

This workshop is offered at the OrCAD Training Center, located in Beaverton, Oregon and in selected North American cities. Onsite training is also available; contact OrCAD DIRECT for more information.

Class size is limited to facilitate maximum interaction between you and the instructor. You are encouraged to bring specific real-world design questions with you to class.

Who Will Benefit

Engineers, designers, and technicians planning to create electronic designs targeted for FPGAs and CPLDs.

Prerequisites

Participants must possess a working knowledge of electronic design, Windows, and standard Windows applications.

Day One: Schematic Entry

  • Setting up a design template
  • Creating a schematic design
  • Placing parts, wires, buses and bus entries
  • Updating part references
  • Adding and updating design properties
  • Building hierarchical designs
Days Two and Three: VHDL
  • Basic modeling constructs
  • Entity and architecture functions
  • Signal declarations
  • Concurrent and sequential design
  • Functions and procedures
  • Flat and hierarchical designs
  • VHDL test benches
  • State machines
Days Four and Five: Using OrCAD Express to design FPGAs
  • Setting up projects and managing design resources
  • Synthesis and optimization
  • Placing and routing an optimized design
  • Using interactive and testbench stimulus
  • Functional, timing, and board-level simulation
  • Detecting timing violations
  • Analyzing simulation results
  • PLD integration
  • PLD symbol generation
More Information

For more information or to register, contact OrCAD Direct at 1-800-671-9505, fax to 503-671-9501, or send E-mail to us at info@orcad.com.


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This page last modified: Tuesday November 04 1997